1. Field of the Invention
The present invention relates to a signal conversion circuit, and particularly to a signal conversion circuit for converting an input differential signal to a single-ended signal.
2. Description of Related Art
In an input/output circuit for inputting/outputting a clock and a data signal, generally a differential signal is widely used so as to reduce noise in an inputting/outputting signal. A circuit receives a differential signal and converts it into a single-phase single-ended signal to supply to an internal circuit and the like.
FIG. 6 shows a configuration of a signal conversion circuit for converting a differential signal into a single-ended signal according to a conventional technique. As shown in the FIG. 6, the conventional signal conversion circuit includes a differential amplifier 610, and inverters 620 and 630.
As differential signals, an input signal SIN and an inverted input signal SINB are inputted to input terminals 601 and 602. The differential amplifier 610 converts differential signals into a single-ended signal Sa. The single-ended signal Sa is repeatedly inverted by the inverters 620 and 630, and an output signal SOUT is outputted from an output terminal 603.
In the differential amplifier 610, a P-channel MOS transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) P611 and an N-channel MOS transistor N611, are connected in series, and a P-channel transistor P612 and an N-channel MOS transistor N612 are connected in series. The P-channel MOS transistor P611 and the P-channel MOS transistor P612 are connected to form a current mirror circuit. The inverters 620 and 630 are comprised of P-channel MOS transistors P621 and P631, and N-channel MOS transistors N621 and N631 respectively.
FIG. 7 illustrates another configuration of a signal conversion circuit according to a conventional technique. As shown in Fig.7, the conventional signal conversion circuit includes a differential amplifier 710 and inverters 720, 730, and 740.
An input signal SIN and an inverted input signal SINB are inputted to the input terminals 701 and 702. The differential amplifier 710 converts the input signals to a single-ended signal Sa. The single-ended signal repeatedly inverted by the inverters 720 and 730, and an output signal SOUT is outputted from an output terminal 703. The inverter 740 is a dummy circuit for balancing an output from the differential amplifier 710.
As a conventional signal conversion circuit, a technique disclosed in Japanese Unexamined Patent Application Publication No. 10-13210 is well known. The technique disclosed in Japanese Unexamined Patent Application Publication No. 10-13210 adjusts a duty ratio by detecting a voltage that differential signals cross over and generating an offset signal. In this case, a circuit for detecting a cross-over voltage and generating an offset signal is needed, thereby complicating the circuit and increasing a size of the circuit.
However with a conventional signal conversion circuit shown in FIGS. 6 and 7, an error in duty ratio could be generated in a single-ended signal that is converted from a differential signal.
This issue is described in detail with reference to FIGS. 8A to 9C. FIGS. 8A to 8C show waveforms of signals for a conventional signal conversion circuit. For example an input signal SIN and an inverted input signal SINB, which are shown in FIG. 8A are inputted to a conventional signal conversion circuit.
In response to the input signal SIN, the N-channel MOS transistor N611 becomes conductive, a current flows in the P-channel MOS transistor P611, and a drain current flows between source-drain of the P-channel MOS transistor P612 as well. Further, in response to the inverted input signal SINB, the N-channel MOS transistor N612 becomes conductive and a drain current flows between drain-source of the N-channel MOS transistor N612. Then a signal Sa is generated from a relation between the drain current of the P-channel MOS transistor P612 and the drain current of the N-channel MOS transistor N612.
Accordingly as shown in FIG. 8B, at a falling edge of the input signal SIN (rising edge of the inverted input signal SINB), a level of the signal Sa reduces as only the N-channel MOS transistor N612 operates, a falling edge of the signal Sa occurs at an almost the same timing as a falling edge of the input signal SIN. However at a rising edge of the input signal SIN, a level of the signal Sa increases as three transistors, the N-channel MOS transistor N611, the P-channel MOS transistors P611 and P612, operates, thus a timing of a rising edge of the signal Sa delays from a timing of a rising edge of the input signal SIN. A difference in timings of a rising edge of the signal Sa and a rising edge of the input signal SIN is larger than a difference in timings of a falling edge of the signal Sa and a falling edge of the input signal SIN. That is, the signal Sa has a similar falling edge timing with the signal SIN whereas a rising timing is delayed, thereby making a pulse width narrower.
The signal Sa is inverted by the inverters 620 and 630. As a result, as shown in FIG. 8C, a duty ratio of the output signal SOUT is smaller than the input signal SIN by an error β.
An output waveform is formed in a similar manner for a conventional signal conversion circuit shown in FIG. 7. At a rising edge of the input signal SIN, a drain potential of the N-channel MOS transistor N711 falls, and a level of the signal Sa increases by the P-channel MOS transistor P712 being operated, accordingly a timing of the rising edge of the signal Sa delays from that of the input signal SIN. On the other hand at a falling edge of the input signal SIN, a level of the signal Sa decreases as only the N-channel MOS transistor P712 being operated, accordingly a timing of the falling edge of the signal Sa is almost the same as that of the input signal SIN, forming waveforms as in FIGS. 8B and 8C.
In case of inverting N-channel MOS transistors for P-channel MOS transistors to configure the conventional signal conversion circuits in FIGS. 6 and 7, waveforms are formed as in FIGS. 9A to 9C. As shown in FIGS. 9A to 9C, waveforms are formed in an opposite manner to FIGS. 8A to 8C. Specifically as shown in FIG. 9B, the signal Sa that is outputted from a differential amplifier rises almost at the same timing as a rising edge of the input signal SIN, and a falling edge timing delays from that of the input signal SIN. Accordingly as shown in FIG. 9C, a duty ratio for a waveform of the output signal SOUT is larger by the error β.
Not only by a delay in a timing of a signal, an error in duty ratio is generated when operating characteristics of P-channel MOS transistors and N-channel MOS transistors in a differential amplifier are imbalanced due to variations in production and an environment change such as a change in temperature. In this case, such an error is generated because of a difference in slopes of a rising edge and a falling edge of the signal Sa. For example FIGS. 10A to 10C illustrates an example in a case a rising edge slope of the signal Sa is less steep than a falling edge slope of the signal Sa. If a rising edge slope of the signal Sa becomes less steep, a rising edge of the output signal SOUT is delayed, thereby making a duty ratio of the output signal SOUT be smaller by the error β, in a similar manner as in FIGS. 8A to 8C. On the other hand FIGS. 11A to 11C illustrates an example in a case a falling edge slope of the signal Sa is less steep than a rising edge slope of the signal Sa. If a falling edge slope of the signal Sa becomes less steep, a falling edge of the output signal SOUT is delayed, thereby making a duty ratio of the output signal SOUT be larger by the error β, in a similar manner as in FIGS. 9A to 9C.
As described in the foregoing, in a conventional signal conversion circuit, a single-ended signal with a duty ratio smaller or larger by an error is outputted, due to a configuration of a differential amplifier, a variation in production tolerance, or an environment change including a change in temperature and the like.